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0adb448ebbbeb44ee048c4e177cb3f9d25a94afcMerge pull request #19 from drom/master
RRazer6 committed 8 years ago
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ed818b99bef541080fea0e3d61beceebcd93657fMerge pull request #21 from DragonForker/bugfix-typo
RRazer6 committed 8 years ago
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0f0d9161058c21db7676c46ffdbebc21edc38839fix(snippets): rectify '}' missing in if-else
ssabertazimi committed 8 years ago
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1fab358757a112e83452ac381dca928cb52554a8broke single <= operator match into separate < and = ; it fixes the issue with FiraCode font thinking that Verilog non-blocking assignment operator is less-or-equal operator like in other languages and replasing it with inappropriate ligature
ddrom committed 8 years ago
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49dfe3c8938d647542f73552e87d721b0dfce9f7Merge pull request #17 from scott-rosenbalm/match_unsized_literals
RRazer6 committed 8 years ago
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d1ab2247c8e848b1b3e9d0e1702fe579e0347489Added unsized_integer to grammar.
sscott-rosenbalm committed 8 years ago