m
mattvenn
Engineer and Science Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member.
443 repositories
608 followers
Valencia, Spain
Repositories
Select a repository to view its commits, contributors, and more.public
awesome-opensource-asic-resources
306
41
1
Updated 13 hours ago
public
basic-ecp5-pcb
Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
Verilog
102
23
4
Updated 19 days ago
public
teensy-audio-fx
Playable effects modeled on the Teenage Engineering Pocket operator series. Featuring Teensy 4 for audio processing.
C++
74
7
7
Updated 20 days ago
public
fpga-sdft
sliding DFT for FPGA, targetting Lattice ICE40 1k
Verilog
73
16
1
Updated a month ago
public
cad
cad files for cnc machining
Python
68
30
1
Updated 2 months ago
public
first-fpga-pcb
FPGA dev board based on Lattice iCE40 8k
Verilog
67
15
0
Updated a month ago
public
vga-clock
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Verilog
59
11
1
Updated 2 months ago
public
wokwi-verilog-gds-test
Verilog
54
20
3
Updated 2 months ago
public
multi_project_tools
tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
Python
35
14
16
Updated 3 months ago
public
flipflop_demo
Flip flop setup, hold & metastability explorer tool
Jupyter Notebook
32
5
0
Updated 2 months ago
public
ws2812-core
verilog core for ws2812 leds
Verilog
32
2
0
Updated 2 months ago
public
vga_clock_pcb
Open source hardware down to the chip level!
30
3
1
Updated 5 months ago