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ws2812-core

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Commits

List of commits on branch master.
Unverified
1340a643dab6eed64d586b8d16f350d766c72f9b

ws2812 cocotb test

mmattvenn committed 3 years ago
Unverified
0c9c11a5c12cdf0a7015269b1440e8dadf22f4f6

remove formal for asic flow

mmattvenn committed 3 years ago
Unverified
776a4d527ff8af7ac508a334bb1ef970df6f5848

default clock is 10mhz

mmattvenn committed 4 years ago
Unverified
9a3298471a8004dcdfb84ec779b2cbfe33fab655

remove messages about memory bypass

mmattvenn committed 4 years ago
Unverified
a737601323154a2a6b6c9dc70c4095352f3259af

remove initial values

mmattvenn committed 4 years ago
Unverified
361efd94c3d119ceba3e5b7c25389b5dc6b24a02

cocotb sim and end with default_nettype wire

mmattvenn committed 4 years ago

README

The README file for this repository.

WS2812 core

very simple WS2812 LED driver written in Verilog. Demonstrates timing is working.

  • Parameter NUM_LEDS sets the number of LEDs in the chain (up to 255)
  • Data is RGB format, 24 bits.
  • Data for each LED is loaded with the write signal
  • expects clock to be 12 MHz

ws2812

Makefile

make debug

Use iverilog to run the testbench and show the results with gtkwave

gtkwave

make formal

Use symbiyosys to formally prove certain aspects of the core

make prog

Synthesise and program bitstream to 8k dev board.